1. Field of the Invention
The present invention relates to a fault distribution analyzing system which analyzes a distribution of fault elements of a semiconductor integrated circuit in which circuit elements are arranged regularly.
2. Description of the Related Art
When a semiconductor integrated circuit has regularly arranged circuit elements and a distribution of fault circuit elements contained in the semiconductor integrated circuit is analyzed, the distribution of fault elements can be visually grasped if the positions of the fault elements are recorded. For example, when the circuit elements are divided into blocks and all of the circuit elements contained in one of the blocks are in failure, the block can be determined to be fault. When two adjacent circuit elements are in failure, the 2-bit pair can be determined to be in failure. Also, when one circuit element is independently in failure, the bit can be determined to be in failure. Moreover, when the neighbor elements are in failure massively, a bit group can be determined to be in failure.
The analysis of the distribution of fault elements is called a bit map analysis. The analysis is especially effective when the distribution of fault elements contained in a semiconductor integrated circuit such as a memory LSI or a memory mounting type logic LSI is analyzed. However, the number of elements contained in one semiconductor integrated circuit reaches 10,000,000 or more with the high integration of the semiconductor integrated circuit in recent years. For this reason, it is difficult for an operator to carry out the whole analysis of the distribution of fault elements based on the bit map analysis. Therefore, the technique for automatically analyzing the distribution of fault elements contained in the semiconductor integrated circuit is proposed in Japanese Laid Open Patent Application (JP-A-showa 61-23327) and Japanese Laid Open Patent Application (JP-A-Heisei 1-216278).
However, there are the following problems in the above-mentioned conventional examples of fault distribution analyzing apparatus.
First, it is difficult to determine whether fault elements distributed in a low density in a wide area over the whole semiconductor integrated circuit shows an irregular distribution or is contained in a regular distribution. Generally, when an analysis technical expert analyzes the distribution of fault elements contained in the semiconductor integrated circuit, the analysis technical expert observes the whole distribution at a low magnification and determines an area with a high fault element density. Then, the analysis technical expert observes the determined area at a high magnification and determines a correct position of the fault element and the regularity of the distribution of fault elements. However, when the fault elements are distributed in a low density in the wide area, the observation area at the high magnification gets wide. Therefore, the analysis by the analysis technical expert is difficult actually.
Second, it is difficult to find the period of the regularity, even when the regularity is discovered in the distribution of fault elements. The reason is that even if a position coordinate frequency distribution of fault elements is determined, the position coordinate range is wide so that the number of fault elements for position coordinate is 1 or a few. Also, this is because the distribution of the fault elements is low in density and is wide in area. In this way, it is difficult to correctly determine the period of the distributions of fault elements.
Third, there is another problem that the distribution of fault elements cannot be stored in the storage and correctly searched by a computer. That is, when the position coordinate of each fault element is to be searched, the number of fault element increases so that the data to be stored has become enormous in case of a semiconductor integrated circuit of a high integration. For this reason, because a storage unit had been saturated at a short time, the conventional fault distribution analyzing apparatus cannot be used in practical use.
On the other hand, a system searching the ratio of the number of fault elements and all the elements is known. However, in this system, a spatial distribution of fault elements cannot be represented, because the system does not contain the data indicative of the position coordinate of the fault element.
Moreover, a system is known which uses a histogram in which the number of fault elements is counted in accordance with the position coordinate. However, there are not distributions in which histograms are completely coincident with each other. Also, the pattern of the histogram becomes different in accordance with the increase of elements in a semiconductor integrated circuit. Therefore, it is difficult to search the histogram having the same pattern.
In conjunction with the above description, method of manufacturing an integrated circuit is disclosed in Japanese Examined Patent application (JP-B-Heisei 5-77178). This reference is directed to a method of manufacturing an integrated circuit which sometimes possibly contains any fault on a manufacturing process. The fault cannot be visually detected or requires an excessive long visual test for the detection. In this reference, a data base is produced to show a response which is caused by a specific fault of a type in response to a series of electric test signals. The series of electric test signals are applied to a manufactured integrated circuit. When any fault is detected, the manufacturing condition is examined so as to clearly specify the fault. Thus, the fault is avoided.
Also, a fault analyzing system of a semiconductor circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-221156). In this reference, the fault analyzing system (101) carries out analysis based on a data obtained through an alien substance test (102) and an outward appearance test (103) in a manufacturing process (111), a data obtained through a final wafer test (112) and a data obtained through a fail bit (FB) analysis system (105). The fail bit analysis system (105) extracts a fault position and a fault inducing position from a distribution of fail bits, using the data obtained through the final wafer test (112) and an LSI design data (107). Then, the fail bit analysis system (105) refers to a fault cause now-how data (108) to carry out estimation (113) of a fault cause. An observing unit (109) observes the fault position and the fault inducing position transferred from the fail bit analysis system (105) to specify the fault cause and a fault process. An analysis unit (110) carries out analysis of composition of an alien substance detected by the observing unit (109) to specify the fault cause and the fault process.
Also, a method of detecting and estimating a dot pattern is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-270012). In this reference, a dot pattern is spatially and discretely in a multi-dimensional coordinate system. Each of dots of the pattern takes either of two identifiable states. A measuring unit records a coordinate value and the state value of each dot of the dot pattern. A memory of a computer stores data corresponding to the coordinate value and state value of each dot. Coordinate counters are determined based on the stored data. A n-dimensional vector composed of components formed of the values of the determined coordinate counters is inputted to a neuron circuit network. The neuron circuit network compare the inputted vector and a reference vector corresponding to a reference dot pattern to calculate an output vector. A classification data of the measured dot pattern is outputted based on the output vector.
Also, a pattern test method is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-89931). In this reference, a concerned point (101) and comparison points (102a to 102d) distanced from the concerned point by a repetition pitch are cross-compared to extract comparison points having any difference as fault candidates. Thus, points having 2-dimensional, X-direction or Y-direction repetition can be tested. Thus, a fault point is detected.
Therefore, an object of the present invention is to provide a method of analyzing a distribution of fault elements contained in a semiconductor integrated circuit, in which it is possible to analyze a distribution of fault elements contained in the semiconductor integrated circuit, a fault distribution analyzing system for the same, and a recording medium in which a program for executing the method is stored.
Another object of the present invention is to provide a method of analyzing a distribution of fault elements contained in a semiconductor integrated circuit, in which it is possible to easily determine whether or not a distribution of fault elements is an irregular distribution, a fault distribution analyzing system for the same, and a recording medium in which a program for executing the method is stored.
Still another object of the present invention is to provide a method of analyzing a distribution of fault elements contained in a semiconductor integrated circuit, in which it is possible to determine whether a distribution of fault elements contains a regular distribution, a fault distribution analyzing system for the same, and a recording medium in which a program for executing the method is stored.
Yet still another object of the present invention is to provide a method of analyzing a distribution of fault elements contained in a semiconductor integrated circuit, in which it is possible to determine a period in a regular distribution when a distribution of fault elements contains the regular distribution, a fault distribution analyzing system for the same, and a recording medium in which a program for executing the method is stored.
In order to achieve an aspect of the present invention, a method of analyzing a distribution of fault elements is applied to a semiconductor integrated circuit including a plurality of elements which are repeatedly arranged in a pitch of one length unit in a specific direction. The method is accomplished by generating a position of each of fault elements in the semiconductor integrated circuit, by performing a first determination of whether an appearance expectation function value is larger than a reference value, for each of divisors of the number of length units between fault elements, the number of length units being larger than one length unit, by performing a second determination of whether a distribution of the fault elements includes a regular distribution, based on the appearance expectation function value and a reference value, and by representing the determining result of the second determination.
Here, in the method, a third determination of a period of the fault elements in the regular distribution contained in the distribution of fault elements may be carried out based on the appearance expectation function values, and then the determined period of the fault elements may be represented.
Also, in the performing a second determination, a record of the appearance expectation function value for each of the divisors and a date and time data may be stored in a data base. In this case, data indicative of the distribution of fault elements is preferably stored in the data base in association with the record. Also, the data base may be searched in response to a search instruction with a target divisor to retrieve the appearance expectation function values for the target divisor and the date and time data corresponding to the appearance expectation function values, to represent the searched appearance expectation function values for the target divisor and the date and time data corresponding to the searched appearance expectation function values.
Also, a third determination of a period of the fault elements in the regular distribution contained in the distribution of fault elements may be performed based on the appearance expectation function values to store the determined period of the fault elements in the data base in addition to the record of the appearance expectation function value for each of the divisors and the date and time data. Also, in the performing a third determination, data indicative of the distribution of fault elements may be stored in the data base in association with the record and the determined period. In addition, the data base may be searched in response to a search instruction with a target divisor to retrieve the appearance expectation function values for the target divisor, the date and time data corresponding to the appearance expectation function values and the determined period of the fault elements, to represent the searched appearance expectation function values for the target divisor and the date and time data corresponding to the appearance expectation function values and the determined period of the fault elements.
The reference value is 1, the performing a first determination includes:
calculating an interval between optional two of all the fault elements contained in the semiconductor integrated circuit;
calculating the number of intervals other than 0, as a combination count;
calculating divisors of each of the intervals larger than 1, and for calculating an appearance probability for each of the divisors based on the number of times of appearance of each of the divisors and the combination count; and
calculating the appearance expectation function value for each of the divisors based on the corresponding one of the appearance probabilities and the each divisors. In this case, the calculating the appearance expectation function value may include multiplying each of the appearance probabilities with corresponding one of the divisors, to calculate the appearance expectation function value.
Also, the method may further include:
determining the largest one of the appearance expectation function values and the next largest one of the appearance expectation function values;
determining an absolute value of a difference between a first one of the divisors corresponding to the largest appearance expectation function value and a second one of the divisors corresponding to the next largest appearance expectation function value; and
determining a fact that the distribution of fault elements contains a regular distribution with a period based on the absolute value of the difference. In this case, the determining a fact includes:
determining a fact that the distribution of fault elements contains the regular distribution with the period having the first divisor, when the absolute value of the difference is equal to the first divisor. Also, the determining a fact includes:
determining a fact that the distribution of fault elements contains the regular distribution with the period, when the absolute value of the difference is not equal to the first divisor, but when the absolute value of the difference is within a predetermined value.
In order to achieve another aspect of the present invention, a fault distribution analyzing system of a semiconductor integrated circuit including a plurality of elements which are repeatedly arranged in a pitch of one length unit in a specific direction, includes an output unit, and an input unit and a first processor. The input unit supplies a position of each of fault elements in the semiconductor integrated circuit. The first processor determines whether an appearance expectation function value is larger than a reference value, for each of divisors of the number of length units between fault elements, the number of length units being larger than one length unit; determines that a distribution of the fault elements includes a regular distribution, when the appearance expectation function value is larger than the reference value; and outputs the determining result of the second determining means to the output unit.
The fault distribution analyzing system may further include a second processor which determines a period of the fault elements in the regular distribution contained in the distribution of fault elements based on the appearance expectation function values; and outputs the determined period of the fault elements to the output unit. In this case, the fault distribution analyzing system may further include a third processor which has a data base, and stores a record of the appearance expectation function value for each of the divisors and a date and time data in the data base.
In this case, the third processor stores data indicative of the distribution of fault elements in the data base in association with the record. Also, the third processor may search the data base in response to a search instruction with a target divisor to retrieve the appearance expectation function values for the target divisor and the date and time data corresponding to the appearance expectation function values; and outputs the searched appearance expectation function values for the target divisor and the date and time data corresponding to the searched appearance expectation function values to the output unit.
Also, the third processor may determine a period of the fault elements in the regular distribution contained in the distribution of fault elements based on the appearance expectation function values; and store the determined period of the fault elements in the data base in addition to the record of the appearance expectation function value for each of the divisors and the date and time data. In this case, the third processor stores data indicative of the distribution of fault elements in the data base in association with the record and the determined period. Also, the third processor may search the data base in response to a search instruction with a target divisor to retrieve the appearance expectation function values for the target divisor, the date and time data corresponding to the appearance expectation function values and the determined period of the fault elements; and outputs the searched appearance expectation function values for the target divisor and the date and time data corresponding to the appearance expectation function values and the determined period of the fault elements to the output unit.
Also, when the reference value is 1, the first processor may calculate an interval between optional two of all the fault elements contained in the semiconductor integrated circuit; calculate the number of intervals other than 0, as a combination count; calculate divisors of each of the intervals larger than 1, and for calculating an appearance probability for each of the divisors based on the number of times of appearance of each of the divisors and the combination count; and calculate the appearance expectation function value for each of the divisors based on the corresponding one of the appearance probabilities and the each divisors. In this case, the first processor multiplies each of the appearance probabilities with corresponding one of the divisors, to calculate the appearance expectation function value.
Also, the second processor may determine the largest one of the appearance expectation function values and the next largest one of the appearance expectation function values; determine an absolute value of a difference between a first one of the divisors corresponding to the largest appearance expectation function value and a second one of the divisors corresponding to the next largest appearance expectation function value; and determine that the distribution of fault elements contains a regular distribution with a period based on the absolute value of the difference. In this case, when the absolute value of the difference is equal to the first divisor, the second processor may determine that the distribution of fault elements contains the regular distribution with the period having the first divisor. Also, when the absolute value of the difference is not equal to the first divisor, but when the absolute value of the difference is within a predetermined value, the second processor may determine that the distribution of fault elements contains the regular distribution with the period.
In order to achieve still another aspect of the present invention, programs to execute the methods described in association with the aspect may be stored in a recording medium or recording media.